Low Power Dynamic Buffer Circuits
نویسندگان
چکیده
منابع مشابه
Low Power Dynamic Buffer Circuits
In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18μm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circui...
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this paper proposes a buffer circuit for footed domino logic circuit. It minimizes redundant switching at the output node. This circuit prevents propagation of precharge pulse to the output node during precharge phase which saves power consumption. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing domino circuit f...
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Four different dynamic circuit techniques are proposed in this paper for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity, and reducing the subthreshold leakage energy of domino logic circuits. A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The thre...
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ژورنال
عنوان ژورنال: International Journal of VLSI Design & Communication Systems
سال: 2012
ISSN: 0976-1527
DOI: 10.5121/vlsic.2012.3505